Data is conventionally provided by a host system, and may conventionally be received on data input pins. For a memory to know when to capture data, the host system may provide a strobe signal, which may cause the memory to capture the data on the input pins. The timing of the strobe signal with respect to the arrival of the data signals may be an important parameter, and may be set to ensure data is captured at a time when the data on the input pins is valid. Valid data may be data that has fully transitioned to a voltage level indicative of a logic state, e.g., a high or low logic state. If, for example, data is captured at a time when it has yet to fully transition, the data stored may not be valid, and an incorrect logic level may be captured and stored. Additionally, the data may only be valid for a limited amount of time. The limited amount of time the data is valid may be referred to as a timing window. Thus, it may be desirable to have the data strobe signal occur, for example, in the middle of the timing window. The difference in timing between the arrival of the data, e.g., the hold time, and the arrival of the strobe signal, e.g., the setup time, may be the timing margin. This is sometimes referred to as the setup/hold time.
The timing margin, however, may become more sensitive for memories operating at low voltages and at high operating speeds. This may be an issue because the margin is much smaller due to the higher operating speeds and the low voltage is more difficult to detect. The low voltages may be more difficult to detect, e.g., discern the intended logic state from, due to the voltage difference between a high and low logic state being small. As such, it may be important to provide enough time for the data signals to fully transition before capturing the data. Additionally, the timing margin may be affected by internal operating parameters of the memory, which may cause the timing margin to drift, resulting in problems related to data capture from an external bus.